I modified my layout in Eagle a bit from the early posting. I decided to drop the copper groundplane to keep the routing on this pretty simple. The blue vertical lines are traces starting with 1mil on the left and ending with 25mil on the right.

I then setup the PCBGCode ULP for wizard to export my board.

I am using a 0.2mm 60 degree vbit that cuts an isolation trace about 12mil wide at 4-5mil deep.

Export script uses 50% of "Etching Tool Size" + the "Default" isolation width to position the cutting bit around the trace. (I found that info on a Google search and it seems to work properly based upon that.)

I think that my smallest trace on this test run was about 2mill. (The left most and right most trace did not appear in my export and I did not count how many traces until after I was milling. --go figure. )

--Click on any of the images to open the larger versions--

I did a test run yesterday and I was able to drive 1-2mil traces too. This seems like the runout on the tooling is pretty decent assuming that I run a test with each tool and document the configuration for future reference.

At this point I could mill through-hole, 1206 SMD, and SOIC components and probably 805 SMD components with the 0.2mm 60 degree vbit. Anything smaller than that and I will need a smaller bit. (The smaller bits for testing are on order and should be here in a few days.)

Based upon this I probably need to adjust my DRC (Design rule checker) too support 12mil isolation spacing until I can further refine my system which seems pretty workable.

I also shot some video of the project today. I plan to edit that together and post it when time permits.

73 de NG0R